Experiment 15 - Cockcroft Walton Multiplier

Engineer Xavier Borg - Blaze Labs Research

Cockcroft and Walton

One of the cheapest and popular ways of generating high voltages at relatively low currents is the classic multistage diode/capacitor voltage multipler, known as Cockcroft Walton multiplier, named after the two men who used this circuit design to be the first to succeed in performing the first nuclear disintegration in 1932. James Douglas Cockcroft and Ernest Thomas Sinton Walton, in fact have used this voltage multiplier cascade for the research which later made them winners of the 1951 Nobel Prize in physics for "Transmutation of atomic nuclei by artificially accelerated atomic particles". Less known is the fact that the circuit was first discovered much earlier, in 1919, by Heinrich Greinacher, a Swiss physicist. For this reason, this doubler cascade is sometimes also referred to as the Greinacher multiplier.
Unlike transformers this method eliminates the requirement for the heavy core and the bulk of insulation/potting required. By using only capacitors and diodes, these voltage multipliers can step up relatively low voltages to extremely high values, while at the same time being far lighter and cheaper than transformers. The biggest advantage of such circuit is that the voltage across each stage of this cascade, is only equal to twice the peak input voltage, so it has the advantage of requiring relatively low cost components and being easy to insulate. One can also tap the output from any stage, like a multitapped transformer. They have various practical applications and find their way in laser systems, CRT tubes, hv power supplies, LCD backlighting, power supplies, x-ray systems, travelling wave tubes, ion pumps, electrostatic systems, air ionisers, particle accelerators, copy machines, scientific instrumentation, oscilloscopes, and many other applications that utilize high voltage DC.


How it works

The Cockcroft Walton or Greinacher design is based on the Half-Wave Series Multiplier, or voltage doubler. In fact, all multiplier circuits can be derived from its operating principles. It mainly consists of a high voltage transformer Ts, a column of smoothing capacitors (C2,C4), a column of coupling capacitors (C1,C3), and a series connection of rectifiers(D1,D2,D3,D4). The following description for the 2 stage CW multiplier, assumes no losses and represents sequential reversals of polarity of the source transformer Ts in the figure shown below. The number of stages is equal to the number of smoothing capacitors between ground and OUT, which in this case are capacitors C2 and C4.

  1. Ts=Negative Peak:C1 charges through D1 to Epk at current ID1
  2. Ts=Positive Peak:Epk of Ts adds arithmetically to existing potential C1, thus C2 charges to 2Epk through D2 at current ID2
  3. Ts=Negative Peak:C3 is charged to 2Epk through D3 at current ID3
  4. Ts=Positive Peak:C4 is charged to 2Epk through D4 at current ID4.
    Output is then 2n*Epk where N = number of stages.

In reality several cycles are required to reach full voltage. The output voltage closely follows the curve of an RC network as shown above. R is the output impedance of the ac source, whilst C is the effective dynamic capacitance of the CW multiplier. This charging occurs only upon switching on the CW multiplier from a discharged state, and does not repeat itself unless the output is short circuited. Most common input AC waveforms are sine waves and square waves.

Designing CW multipliers

TV tripler This is a 3 stage CW multiplier, commonly known as tripler, used in most of the early B&W and colour TV's. The voltage drops rapidly as a function of the output current. In some applications, this is an advantage. The output V/I characteristic is roughly hyperbolic, so it serves well for charging capacitor banks to high voltages at roughly constant charging power. Furthermore, the ripple on the output, particularly at high loads, is quite high.


This is a simulation of a 3 stage CW multiplier. The input is a sinewave 10kV peak voltage. Vn(n003), V(n005) and V(out) are the voltage levels at each stage, referenced to ground. Theoretically, V(out) = 2n*Epk= 2*3*10 = 60kV. As you can see from the above simulation, the loaded output never reaches this value due to the poor voltage regulation of the CW as discussed below.

The output voltage (Eout) of each stage is nominally twice the peak input voltage (Epk). It is relatively easy to step the voltage by one order of magnitude (say 100kV to 1MV) with just 5 stages. This circuit is in fact frequently used to generate megavolts, and as shown above, although the actual components and physical dimensions get larger, the concept remains exactly the same.

 Eout = 2n*Epk - VDrop .... VDrop=0 under no load

For example, in a 3 stage CW, the no load voltage Eout = 2 * 3 * Epk
If Epk was 10 kV, then the output of the circuit would be 60 kV. In practice, the output is lower due to the parameter VDrop, particularly with a large number of stages. Each hv diode drops the voltage across it by about 250v at its rated current and a power loss (250*Idiode) within each diode occurs during each charging cycle. The steady state current Idiode is equal to the steady state load current Iload. For this reason, heat dissipation may become a problem with small diodes, which could be immersed in oil to alleviate this problem. Capacitors tend to be more efficient, and their only concern is their voltage rating.


Regulation and ripple calculations

The voltage drop under load is mostly reactive and can be calculated as:

 VDROP = [Iload/(6fC)] * (4n3 + 3n2 - n)  

where:
Iload is the load current (Amps)
C is the stage capacitance (Farads)
f is the AC frequency (Hz)
n is the number of stages.

Substitiuting for VDROP in the previous equation, we get:

 Eout = 2n*Epk - [Iload/(6fC)] * (4n3 + 3n2 - n)  


Example: A 3 stage CW, driven by a 70kHz peak voltage of 10kV, with capacitors value 390pF, and a load current of 10mA:

VDROP = [Iload/(6fC)] * (4 n3 + 3 n2 - n)
VDROP = 8kV
Eout = 60kV - 8kV = 52kV

The ripple voltage, in the case where all stage capacitances (C1 through C(2*n)) are equal, may be calculated from:

 Eripple = [Iload/(2fC)]*n*(n+1)

In our example:

Eripple = [Iload/(2fC)]*n*(n+1)
Eripple = [10mA/(2*70E3*390E-12)]*3*4 = 2.2kV

So the output voltage will swing between 52kV and 49.8kV. Below is a SPICE simulation of our circuit example, being very close to our calculated ripple value.

As you can see from this equation, the ripple grows quite rapidly as the number of stages increases (as n squared, in fact). A common modification to the design is to make the stage capacitances larger at the bottom, with C1 & C2 = nC, C3 & C4 = (n-1)C, and so forth. In this case, the ripple and voltage drops are given by:

 Eripple = n * Iload/ fC  

 Vdrop = n2 * Iload/ fC 

For the above example, this modification will reduce the ripple voltage from 2.2kV to just 1.1kV, and the voltage drop from 8kV to 3.3kV.

Once a load is connected at the output, the output voltage decreases due to the voltage regulation mentioned above. Also, any small fluctuation of load impedance causes a large fluctuation in the output voltage of the multiplier due to the number of stages involved. For this reason, voltage multipliers are used only in special applications where the load is constant and has a high impedance or where voltage stability is not critical. Some engineers compensate for this fluctuation by incorporating a feedback loop, which varies the input voltage of the Cockcroft Walton multiplier according to the actual output voltage.

For large values of n (≥5), the 3n2 and n terms in the voltage drop equation become small compared to the 4n3. Differentiating the EOUT equation without these negligible terms, with respect to the number of stages and equating to zero to find the peak of the curve, gives an equation for the optimum (integer) number of stages for the equal valued capacitor design:

d/dn{Eout} = d/dn{2n*Epk - [Iload/(6fC)] * (4n3)} = 0
2Epk = Iload/(6fC) * 3 * 4n2

 Noptimum = INT[SQRT( Epk * fC/Iload)]  

If we differentiate the Eout equation, this time including the 3n2 and n terms, we get a more accurate equation, also valid for n<5:

 Noptimum = INT[SQRT(3Iload*(7Iload+48fC*Epk))/(12*Iload) -1/4]  

If we drive our CW with an input voltage Epk=10kV and a load of 10mA, running at 70kHz and 390pF capacitors, Noptimum=INT[5.22]=5 (using the first equation), and Noptimum=INT[4.988]=5 (using the second equation) so we go for a 5 stage CW multiplier.

If we know the driving voltage Epk and the required output voltage Eout, we can also approximate the optimum number of stages from:

 Noptimum = INT[3 EOut/4Epk] *(1)


*(1) Cockcroft Walton Optimum Design Guide by Michel Jullian


The full wave CW

Increasing the frequency can dramatically reduce the ripple, and the voltage drop under load, which accounts for the popularity of driving a multipler stack with a switching power supply. A clever way to reduce ripple is to implement a full wave voltage doubler as shown below. This effectively doubles the number of charging cycles per second, and thus cuts down the voltage drop and ripple factor. The input is usually fed from a centre tapped ac transformer or MOSFET H-bridge circuits.



As with the classical CW, the full wave CW output voltage is given by:

 Eout = 2n*Epk - VDrop

For example, in a 3 stage full wave CW, the open circuit voltage (no voltage drop) : Eout = 2 * 3 * Epk
If Epk was 10 kV, then the open circuit output voltage would be 60 kV.


Regulation and ripple calculations for full wave CW

The voltage drop under load can be calculated as:

 VDROP = [Iload/(6fC)] * (n3 + 2n)

where:
Iload is the load current (Amps)
C is the stage capacitance (Farads)
f is the AC frequency (Hz)
n is the number of stages.

Substitiuting for VDROP in the previous equation, we get:

 Eout = 2n*Epk - [Iload/(6fC)] * (n3 + 2n)


Example: A 3 stage full wave CW, driven by a 70kHz peak voltage of 10kV, with capacitors value 390pF, and a load current of 10mA:

VDROP = [Iload/(6fC)] * (n3 + 2 n)
VDROP = 2kV
Eout = 60kV - 2kV = 58kV

The ripple voltage, in the case where all stage capacitors are equal, may be calculated from:

 Eripple = [Iload/(2fC)]*n

In our example:

Eripple = [Iload/(2fC)]*n
Eripple = [10mA/(2*70E3*390E-12)]*3 = 550v

The optimum number of stages for a given output and input voltage is given by:

 Noptimum = INT[0.521 EOut/Epk]




Construction of my 5 stage CW multiplier rated 75 kV output at no load
Used to power our Super V1.0 Thruster


See also:

BlazeLabs Resonant Multipliers
CW / BRM Online Java calculator




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